Related art semiconductor manufacturing technologies may cause plasma damage to an edge portion of a gate insulating layer during an etching process for forming a gate. Such plasma damage may lead to a hot carrier effect, and may degrade characteristics of the gate insulating layer and lower reliability of semiconductor devices. In addition, a junction formed through low-density ion implantation may be partially overlapped with a lower portion of the gate insulating layer due to ion diffusion into the lower portion of the gate insulating layer. Thus, gate induced drain leakage (GIDL) characteristics are degraded and parasitic capacitance may be created, so that performance of the semiconductor device may be degraded.
A related art device will be described with reference to accompanying drawings. FIGS. 1A to 1C are sectional diagrams illustrating a related art gate structure of a semiconductor device and a method of manufacturing the same.
Referring to FIG. 1A, a shallow trench isolation (STI) process and a well forming process may be performed relative to a silicon substrate. Gate insulating layer 11 and gate conductive layer 12 may be deposited and patterned on a silicon substrate 10. Plasma damage may be caused to edge portion 11a of gate insulating layer 11 due to an etching process. Reliability of any semiconductor device may thereby be lowered.
Referring to FIG. 1B, thin oxide layer 13 may be deposited on the silicon substrate 10 and an ion implantation process may be performed to form low-density source/drain junction 14. Thin oxide layer 13 may be a temporal oxide layer, which may be temporarily formed to protect a surface of the silicon substrate.
However, a deposition process and a removal process for temporal oxide layer 13 may further cause damage to gate insulating layer 11, and may degrade a reliability of the semiconductor device.
In addition, source/drain junction 14 formed through the low-density ion implantation may be partially overlapped with a lower portion of gate insulating layer 11 due to ion diffusion.
As described above, such an overlap may be a factor that degrades a performance of the semiconductor device.
Referring to FIG. 1C, temporal oxide layer 13 may be removed. A spacer insulating layer may be deposited and then gate spacer 15 may be formed by performing an anisotropic etching process. Gate spacer 15 may include oxide 15a and nitride 15b. High-density ion implantation process may be performed and may form high-density source/drain junction 16. Various other components, such as an interlayer dielectric layer, a metal interconnection, etc., may be formed through subsequent processes.